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Disambiguation of "Pan, Po-Cheng"

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On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts.

, , , , , and . SMACD, page 181-184. IEEE, (2018)

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Po-Cheng Huang

Fong Cheng Pan

Cheng-Yung Cheng

Po Leung

Xiaoqing Pan

 

Other publications of authors with the same name

Efficient analog layout prototyping by layout reuse with routing preservation., , , , and . ICCAD, page 40-47. IEEE, (2013)An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis., , and . DAC, page 232. ACM, (2019)On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts., , , , , and . SMACD, page 181-184. IEEE, (2018)Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping., , and . ISQED, page 777-784. IEEE, (2011)Analog placement with current flow and symmetry constraints using PCP-SP., , , , , and . DAC, page 10:1-10:6. ACM, (2018)R2P: Recomposition and Retargeting of Photographic Images., , , and . ACM Multimedia, page 927-930. ACM, (2015)A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (9): 1373-1386 (2015)An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming., , , , , and . VLSI-DAT, page 1-4. IEEE, (2014)Configurable analog routing methodology via technology and design constraint unification., , , , and . ICCAD, page 620-626. ACM, (2012)PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design., , and . DATE, page 1849-1854. EDA Consortium San Jose, CA, USA / ACM DL, (2013)