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The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks.

, and . FCCM, page 303-. IEEE Computer Society, (2002)

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Should the academic community launch an open-source FPGA device and tools effort?: evening panel.. FPGA, page 3-4. ACM, (2011)OLAF'17: Third International Workshop on Overlay Architectures for FPGAs., and . FPGA, page 1. ACM, (2017)A Comparison of the AES Candidates Amenability to FPGA Implementation., and . AES Candidate Conference, page 28-39. National Institute of Standards and Technology,, (2000)Instruction-Level Parallelism for Reconfigurable Computing., and . FPL, volume 1482 of Lecture Notes in Computer Science, page 248-257. Springer, (1998)Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , and 1 other author(s). CoRR, (2018)SPADES: A Productive Design Flow for Versal Programmable Logic., , , and . FPL, page 65-71. IEEE, (2023)Datapath-oriented FPGA mapping and placement for configurable computing., and . FCCM, page 234-235. IEEE Computer Society, (1997)The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks., and . FCCM, page 303-. IEEE Computer Society, (2002)Reconfigurable computing in the era of post-silicon scaling panel discussion., , , , , , and . FCCM, IEEE Computer Society, (2013)The Design And Application Of A High-End Reconfigurable Computing System., , , and . ERSA, page 129-136. CSREA Press, (2005)