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Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms.

H. Esmaeilzadeh, S. Ghodrati, A. Kahng, J. Kim, S. Kinzer, S. Kundu, R. Mahapatra, S. Manasi, S. Sapatnekar, Z. Wang, and Z. Zeng. MLCAD, page 119-126. ACM / IEEE, (2022)

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Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Chhatwani

Sachin Kumar

Other publications of authors with the same name

Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits.S. Sapatnekar, and R. Deokar. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (10): 1237-1248 (1996)A practical methodology for early buffer and wire resource allocation.C. Alpert, J. Hu, S. Sapatnekar, and P. Villarrubia. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (5): 573-583 (2003)OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis.V. Chhabria, and S. Sapatnekar. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3515-3528 (2022)Incremental solution of power grids using random walks.B. Boghrati, and S. Sapatnekar. ASP-DAC, page 757-762. IEEE, (2010)A retargetable and accurate methodology for logic-IP-internal electromigration assessment.P. Jain, S. Sapatnekar, and J. Cortadella. ASP-DAC, page 346-351. IEEE, (2015)A fixed-die floorplanning algorithm using an analytical approach.Y. Zhan, Y. Feng, and S. Sapatnekar. ASP-DAC, page 771-776. IEEE, (2006)Circuit delay variability due to wire resistance evolution under AC electromigration.V. Mishra, and S. Sapatnekar. IRPS, page 3. IEEE, (2015)Fast Mapping-Based High-Level Synthesis of Pipelined Circuits.C. Li, S. Sapatnekar, and J. Hu. ISQED, page 33-38. IEEE, (2019)The impact of electromigration in copper interconnects on power grid integrity.V. Mishra, and S. Sapatnekar. DAC, page 88:1-88:6. ACM, (2013)Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.V. Nookala, D. Lilja, and S. Sapatnekar. ISLPED, page 298-303. ACM, (2006)

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Disambiguation of "Sapatnekar, Sachin S."

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Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms.

Please choose a person to relate this publication to

Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Chhatwani

Sachin Kumar

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Sapatnekar, Sachin S."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms.

Please choose a person to relate this publication to

Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Chhatwani

Sachin Kumar

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms.