( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.

, , , , , и . FCCM, стр. 17-24. IEEE Computer Society, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Anne Canis

Martin Canis

Martin Canis

Konrad Canis

Johannes Canisius

 

Другие публикации лиц с тем же именем

Profiling-driven multi-cycling in FPGA high-level synthesis., , , , , и . DATE, стр. 31-36. ACM, (2015)LegUp: high-level synthesis for FPGA-based processor/accelerator systems., , , , , , , и . FPGA, стр. 33-36. ACM, (2011)Multi-pumping for resource reduction in FPGA high-level synthesis., , и . DATE, стр. 194-197. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Low-cost hardware profiling of run-time and energy in FPGA embedded processors., , , и . ASAP, стр. 61-68. IEEE Computer Society, (2011)From C to Blokus Duo with LegUp high-level synthesis., , , , , , , , , и 2 other автор(ы). FPT, стр. 486-489. IEEE, (2013)Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems., , , , , и . FCCM, стр. 17-24. IEEE Computer Society, (2012)The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs., , , , , , и . FCCM, стр. 89-96. IEEE Computer Society, (2013)From software to accelerators with LegUp high-level synthesis., , , , , , , , , и 2 other автор(ы). CASES, стр. 18:1-18:9. IEEE, (2013)Modulo SDC scheduling with recurrence minimization in high-level synthesis., , и . FPL, стр. 1-8. IEEE, (2014)High-level synthesis with LegUp: a crash course for users and researchers., , , и . FPGA, стр. 7-8. ACM, (2013)