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Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.

, , , , , and . FCCM, page 17-24. IEEE Computer Society, (2012)

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Recursive circuit clustering for minimum delay and area., and . FPGA, page 242. ACM, (2003)Constrained clock shifting for field programmable gate arrays., and . FPGA, page 121-126. ACM, (2002)Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 232-241. Springer, (2002)From C to Blokus Duo with LegUp high-level synthesis., , , , , , , , , and 2 other author(s). FPT, page 486-489. IEEE, (2013)Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware., , and . FPT, page 152-159. IEEE, (2015)FPGA and CPLD Architectures: A Tutorial., and . IEEE Des. Test Comput., 13 (2): 42-57 (1996)Improving FPGA Routing Architectures Using Architecture and CAD Interactions., , and . ICCD, page 99-104. IEEE Computer Society, (1992)Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs., , , and . ICCAD, page 135-142. ACM, (2006)FPGA PLB Evaluation using Quantified Boolean Satisfiability., , and . FPL, page 19-24. IEEE, (2005)Two-stage physical synthesis for FPGAs., , and . CICC, page 171-178. IEEE, (2005)