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Disambiguation of "Rajski, Janusz"

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Low power compression utilizing clock-gating.

, , and . ITC, page 1-8. IEEE Computer Society, (2011)

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Janusz Panzer

Janusz Gatniejewski

Janusz Rat

Janusz Surzykiewicz

Janusz Bogdanowicz

 

Other publications of authors with the same name

Self-test methodology for at-speed test of crosstalk in chip interconnects., , and . DAC, page 619-624. ACM, (2000)Built-In Self-Test for Systems on Silicon., , and . VLSI Design, page 609-610. IEEE Computer Society, (1999)Embedded deterministic test points for compact cell-aware tests., , , , , , , , , and . ITC, page 1-8. IEEE, (2015)GEMINI-a logic system for fault diagnosis based on set functions.. FTCS, page 292-297. IEEE Computer Society, (1988)On necessary and nonconflicting assignments in algorithmic test pattern generation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (4): 515-530 (1994)DIST: Deterministic In-System Test with X-masking., , , and . ITC, page 20-27. IEEE, (2022)Test Generation for an Iterative Design Flow with RTL Changes., , , and . ITC, page 305-313. IEEE, (2022)Diagnosis with Limited Failure Information., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)On Using Implied Values in EDT-based Test Compression., , , , and . DAC, page 11:1-11:6. ACM, (2014)Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits., and . ITC, page 473-482. IEEE Computer Society, (1991)