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A BIST approach for very deep sub-micron (VDSM) defects.

, , , и . ITC, стр. 283-291. IEEE Computer Society, (2000)

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Michinobu Doi

 

Другие публикации лиц с тем же именем

Accelerated Test Points Selection Method for Scan-Based BIST., , и . Asian Test Symposium, стр. 359-. IEEE Computer Society, (1997)Low overhead test point insertion for scan-based BIST., , , , и . ITC, стр. 348-357. IEEE Computer Society, (1999)Application of High-Quality Built-In Test to Industrial Designs., , , , , и . ITC, стр. 1003-1012. IEEE Computer Society, (2002)Hardware Overhead Reduction for Memory BIST., , , и . ITC, стр. 1. IEEE Computer Society, (2008)A parallel sequential test generation system DESCARTES based on real-valued logic simulation., , и . Asian Test Symposium, стр. 252-258. IEEE Computer Society, (1995)Test Generation for Multiple-Threshold Gate-Delay Fault Model., , , , и . Asian Test Symposium, стр. 244-. IEEE Computer Society, (2001)Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs., , , , , и . IEICE Trans. Electron., 96-C (1): 108-114 (2013)A BIST approach for very deep sub-micron (VDSM) defects., , , и . ITC, стр. 283-291. IEEE Computer Society, (2000)Enhancing Transition Fault Model for Delay Defect Diagnosis., , , , , , , , и . ATS, стр. 179-184. IEEE Computer Society, (2008)At-Speed Built-in Test for Logic Circuits with Multiple Clocks., , и . Asian Test Symposium, стр. 292-297. IEEE Computer Society, (2002)