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MT-SBST: Self-test optimization in multithreaded multicore architectures.

, , , , , and . ITC, page 734-743. IEEE Computer Society, (2010)

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Recursive Pseudo-Exhaustive Two-Pattern Generation., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (1): 142-152 (2010)Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units., , , and . IEEE Trans. Computers, 55 (11): 1449-1457 (2006)Anatomy of On-Chip Memory Hardware Fault Effects Across the Layers., and . IEEE Trans. Emerg. Top. Comput., 11 (2): 420-431 (April 2023)Hierarchical synthesis of quantum and reversible architectures., and . Conf. Computing Frontiers, page 13:1-13:8. ACM, (2015)Dependable Multicore Architectures at Nanoscale: The View From Europe., , , , , , , , , and 4 other author(s). IEEE Des. Test, 32 (2): 17-28 (2015)Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures., , and . ITC, page 377-382. IEEE, (2023)Analysis and Characterization of Ultra Low Power Branch Predictors., , , , and . ICCD, page 144-147. IEEE Computer Society, (2018)The functional and performance tolerance of GPUs to permanent faults in registers., , and . IOLTS, page 236-239. IEEE, (2013)Measuring the performance impact of permanent faults in modern microprocessor architectures., , , and . IOLTS, page 181-184. IEEE, (2013)Energy Efficiency of Out-of-Order CPUs: Comparative Study and Microarchitectural Hotspot Characterization of RISC-V Designs., , , and . IISWC, page 216-220. IEEE, (2023)