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ITAP: Idle-Time-Aware Power Management for GPU Execution Units., , , , , , , , , and . ACM Trans. Archit. Code Optim., 16 (1): 3:1-3:26 (2019)DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks., , , , , , , and . CoRR, (2021)BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows., , , , , , , , , and 2 other author(s). HPCA, page 345-358. IEEE, (2021)Architecting a computer with a full optical RAM., , and . ICECS, page 716-719. IEEE, (2016)Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration., , , , , , , , , and . MICRO, page 298-311. IEEE Computer Society, (2018)Temporal frequent value locality., and . ASAP, page 147-152. IEEE Computer Society, (2016)Reducing Solid State Drive Read Latency by Optimizing Read-Retry., , , , , and . CoRR, (2020)HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips., , , , , , , and . MICRO, page 815-834. IEEE, (2022)CODIC: A Low-Cost Substrate for Enabling Custom In-DRAM Functionalities and Optimizations., , , , , , , , , and 3 other author(s). ISCA, page 484-497. IEEE, (2021)FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors., , , , , , , and . MICRO, page 1051-1066. IEEE, (2020)