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Disambiguation of "Matsunaga, Yusuke"

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Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs.

, and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3268-3275 (2009)

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Shinichiro Matsunaga

Yusuke Sugihara

Yusuke Ohta

Yusuke Asai

Yuko Gfeller-Matsunaga

 

Other publications of authors with the same name

A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)., and . FPGA, page 289. ACM, (2010)Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (12): 3451-3460 (2008)An Efficient Equivalence Checker for Combinational Circuits.. DAC, page 629-634. ACM Press, (1996)An Efficient SAT-Attack Algorithm Against Logic Encryption., and . IOLTS, page 44-47. IEEE, (2019)Multi-operand adder synthesis on FPGAs using generalized parallel counters., , and . ASP-DAC, page 337-342. IEEE, (2010)Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs., and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams., , , and . ICCD, page 286-290. IEEE Computer Society, (1990)Development of practical ATPG tool with flexible interface., and . ATS, page 129. IEEE, (2006)Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems., , , , , , , , , and 1 other author(s). SoC, page 137-140. IEEE, (2005)Binding Refinement for Multiplexer Reduction., and . Inf. Media Technol., 4 (2): 190-199 (2009)