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Disambiguation of "Takata, Taiga"

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Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs.

, and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3268-3275 (2009)

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Taiga Nakamura

Taiga Brahm

 

Other publications of authors with the same name

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits., and . IOLTS, page 246-251. IEEE Computer Society, (2011)Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3268-3275 (2009)A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)., and . FPGA, page 289. ACM, (2010)Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs., and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems., , , , , , , , , and 1 other author(s). SoC, page 137-140. IEEE, (2005)Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs., and . ASP-DAC, page 144-147. IEEE, (2008)A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits., and . IPSJ Trans. Syst. LSI Des. Methodol., (2012)Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure., , , , , , , , and . IOLTS, page 151-156. IEEE Computer Society, (2011)An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs., and . ACM Great Lakes Symposium on VLSI, page 351-356. ACM, (2009)A character size optimization technique for throughput enhancement of character projection lithography., , , , , , , , , and 1 other author(s). ISCAS, IEEE, (2006)