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Disambiguation of "Sim, Jae-Yoon"

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A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes.

, , , , , and . IEEE J. Solid State Circuits, 49 (8): 1682-1693 (2014)

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Jae-Han Sim

Jae-Yoon Kim

Unyong Sim

Sim Hägele

Gavin Sim

 

Other publications of authors with the same name

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator., , and . ISOCC, page 68-71. IEEE, (2012)A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio., , , and . A-SSCC, page 325-328. IEEE, (2011)A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering., , , and . ISSCC, page 94-96. IEEE, (2011)An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface., , , , , and . CICC, page 373-376. IEEE, (2007)A voltage-scalable 10-b pipelined ADC with current-mode amplifier., , , , and . CICC, page 1-4. IEEE, (2014)A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (2): 141-145 (2016)A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC., , , , , , , and . IEEE J. Solid State Circuits, 51 (2): 391-400 (2016)A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes., , , , , and . IEEE J. Solid State Circuits, 49 (8): 1682-1693 (2014)An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface., , , , , , , , and . IEEE J. Solid State Circuits, 49 (11): 2618-2630 (2014)