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ArChiVED: Architectural checking via event digests for high performance validation., , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Microarchitectural power modeling techniques for deep sub-micron microprocessors., , , , and . ISLPED, page 212-217. ACM, (2004)SAGA: SystemC acceleration on GPU architectures., , , and . DAC, page 115-120. ACM, (2012)High-radix on-chip networks with low-radix routers., , and . ICCAD, page 289-294. IEEE, (2014)PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis., and . HLDVT, page 54-59. IEEE Computer Society, (2009)Depth-driven verification of simultaneous interfaces., , and . ASP-DAC, page 442-447. IEEE, (2006)Post-silicon debugging for multi-core designs.. ASP-DAC, page 255-258. IEEE, (2010)STACCATO: disjoint support decompositions from BDDs through symbolic kernels., and . ASP-DAC, page 276-279. ACM Press, (2005)Machine learning-based anomaly detection for post-silicon bug diagnosis., , , and . DATE, page 491-496. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs., , , , , , , , and . FCCM, page 88-96. IEEE, (2021)