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Disambiguation of "Kim, Nam Sung"

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Microarchitectural power modeling techniques for deep sub-micron microprocessors.

, , , , and . ISLPED, page 212-217. ACM, (2004)

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Nam-h Kim

Hong-Nam Kim

Nam-Kim Nguyen

Nam-Seog Kim

Jung-Nam Kim

 

Other publications of authors with the same name

Memory scheduling towards high-throughput cooperative heterogeneous computing., , , and . PACT, page 331-342. ACM, (2014)VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency., , , , and . DAC, page 151:1-151:6. ACM, (2016)Bit Serializing a Microprocessor for Ultra-low-power., , , and . ISLPED, page 200-205. ACM, (2016)Microarchitectural power modeling techniques for deep sub-micron microprocessors., , , , and . ISLPED, page 212-217. ACM, (2004)The microarchitecture of a low power register file., and . ISLPED, page 384-389. ACM, (2003)Bit-Parallel Vector Composability for Neural Acceleration., , , , and . DAC, page 1-6. IEEE, (2020)Exploiting OS-Level Memory Offlining for DRAM Power Management., , and . IEEE Comput. Archit. Lett., 18 (2): 141-144 (2019)The conversion from similarity for mobile life-log to euclidean distance., , , , and . ICMLC, page 1087-1091. IEEE, (2013)An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques., , , , , , , , , and 18 other author(s). IEEE J. Solid State Circuits, 56 (1): 212-224 (2021)Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling., , , , , and . VLSID, page 201-206. IEEE, (2020)