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On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function.

, , , , and . SECRYPT, page 270-275. SciTePress, (2012)

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High-performance FPGA implementations of the cryptographic hash function JH., , , and . IET Comput. Digit. Tech., 7 (1): 29-40 (2013)Throughput Optimization of the Cipher Message Authentication Code., , , and . DSP, page 495-498. IEEE, (2007)High performance pipelined FPGA implementation of the SHA-3 hash algorithm., , and . MECO, page 68-71. IEEE, (2015)Evolution of the e-Museum Concept through Exploitation of Cryptographic Algorithms., , , and . EuroMed, volume 7616 of Lecture Notes in Computer Science, page 291-300. Springer, (2012)Pipelined SHA-3 Implementations on FPGA: Architecture and Performance Analysis., , and . CS2@HiPEAC, page 13-18. ACM, (2015)High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach., , , , , and . SECRYPT, page 126-135. SciTePress, (2012)A Robotic System for Home Security Enhancement., , , , and . ICOST, volume 6159 of Lecture Notes in Computer Science, page 43-52. Springer, (2010)Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core., , , , , and . ICECS, page 1180-1183. IEEE, (2006)Hardware implementation of the Totally Self-Checking SHA-256 hash core., , , , and . EUROCON, page 1-5. IEEE, (2015)Design and validation of an agent-based driving simulator., , , and . SummerSim, page 6:1-6:12. ACM, (2018)