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Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.

J. Shi, X. Zhang, P. Ma, W. Pan, P. Li, and Z. Tang. IEEE Trans. Circuits Syst. II Express Briefs, 68 (6): 2152-2156 (2021)

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Xiaoqing Pan

Petra Pan

Weiqing Pan

Alexey Pan

Pan Li

Other publications of authors with the same name

DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.C. Duan, J. Yang, X. He, Y. Qi, Y. Wang, Y. Wang, Z. He, B. Yan, X. Wang, X. Jia and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (3): 906-918 (March 2024)Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.M. Li, J. Yang, Y. Qi, M. Dong, Y. Yang, R. Liu, W. Pan, B. Yu, and W. Zhao. DAC, page 331-336. ACM, (2022)A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers.L. Zheng, Z. Qiu, W. Pan, and Y. Gao. ChinaCom, volume 262 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 374-383. Springer, (2018)Design and Implementation of AS6802 Clock Synchronization System in TTE thernet.J. Dong, Z. Qiu, W. Pan, M. Wu, and J. Cao. ICCCS, page 1005-1010. IEEE, (2021)A Machine Learning Based Approach to Detect Machine Learning Design Patterns.W. Pan, H. Washizaki, N. Yoshioka, Y. Fukazawa, F. Khomh, and Y. Guéhéneuc. APSEC, page 574-578. IEEE, (2023)DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory.C. Duan, J. Yang, X. He, Y. Qi, Y. Wang, Y. Wang, Z. He, B. Yan, X. Wang, X. Jia and 2 other author(s). CoRR, (2023)The High Speed Packet Classification Supporting Multi - Field for Flow Tables in OpenFlow.Z. Qiu, W. Wang, S. Sun, W. Pan, L. Zheng, Y. Gao, and Z. Zhang. CITS, page 1-5. IEEE, (2018)Access mechanism for period flows of non-deterministic end systems for time-sensitive networks.Z. Zhao, L. Gao, W. Pan, Z. Qiu, X. Guo, Y. Gao, and L. Zheng. Comput. Networks, (July 2023)Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.J. Shi, X. Zhang, P. Ma, W. Pan, P. Li, and Z. Tang. IEEE Trans. Circuits Syst. II Express Briefs, 68 (6): 2152-2156 (2021)Design of HIMAC Coprocessor for HINOC3.0.J. Huang, Z. Qiu, W. Pan, J. Li, Z. Gao, B. Han, Z. Xiong, and M. Dong. ICCCS, page 1047-1052. IEEE, (2021)

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Disambiguation of "Pan, Weitao"

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Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.

Please choose a person to relate this publication to

Xiaoqing Pan

Petra Pan

Weiqing Pan

Alexey Pan

Pan Li

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Pan, Weitao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.

Please choose a person to relate this publication to

Xiaoqing Pan

Petra Pan

Weiqing Pan

Alexey Pan

Pan Li

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.