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Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications.

, , and . ICASSP (5), page 17-20. IEEE, (2005)

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A novel memoryless AES cipher architecture for networking applications., , , , and . ISCAS (4), page 333-336. IEEE, (2004)A performance-driven configurable motion estimator for full-search block-matching algorithm., and . ISCAS (2), page 233-236. IEEE, (2004)Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000., , , and . ICASSP (3), page 964-967. IEEE, (2006)Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder., , , and . ICME, page 145-148. IEEE Computer Society, (2008)A high-speed 2-D transform architecture with unique kernel for multi-standard video applications., , and . ISCAS, page 21-24. IEEE, (2008)A high data-reuse architecture with double-slice processing for full-search block-matching algorithm., and . ISCAS (2), page 716-719. IEEE, (2003)18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2015)Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm., , , and . ICME, page 1021-1024. IEEE Computer Society, (2008)VLSI architecture of the reconfigurable computing engine for digital signal processing applications., and . ISCAS (2), page 937-940. IEEE, (2004)Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation., , , and . ISCAS, page 1657-1660. IEEE, (2009)