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Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications.

, , и . ICASSP (5), стр. 17-20. IEEE, (2005)

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Fei Chen

Fei Chen

Fei Chen

Fei Chen

Fei Chen

 

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A novel memoryless AES cipher architecture for networking applications., , , , и . ISCAS (4), стр. 333-336. IEEE, (2004)A performance-driven configurable motion estimator for full-search block-matching algorithm., и . ISCAS (2), стр. 233-236. IEEE, (2004)Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000., , , и . ICASSP (3), стр. 964-967. IEEE, (2006)Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder., , , и . ICME, стр. 145-148. IEEE Computer Society, (2008)A high data-reuse architecture with double-slice processing for full-search block-matching algorithm., и . ISCAS (2), стр. 716-719. IEEE, (2003)A high-speed 2-D transform architecture with unique kernel for multi-standard video applications., , и . ISCAS, стр. 21-24. IEEE, (2008)Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm., , , и . ICME, стр. 1021-1024. IEEE Computer Society, (2008)18.6 A 0.5nJ/pixel 4K H.265/HEVC codec LSI for multi-format smartphone applications., , , , , , , , , и 21 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation., , , и . ISCAS, стр. 1657-1660. IEEE, (2009)A two-way SIMD-based reconfigurable computing architecture for multimedia applications., , , и . ISCAS (5), стр. 4578-4581. IEEE, (2005)