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Disambiguation of "Sohn, Kyomin"

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Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).

, , , , , , , , , , , , , , , , , , and . A-SSCC, page 169-172. IEEE, (2016)

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Johann Söhn

Ewald Söhn

Sigrid Sohn

Janina Söhn

Gerhard Sohn

 

Other publications of authors with the same name

An Architecture of Sparse Length Sum Accelerator in AxDIMM., , , and . AICAS, page 1-4. IEEE, (2022)Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product., , , , , , , , , and 6 other author(s). ISCA, page 43-56. IEEE, (2021)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 330-332. IEEE, (2020)Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)., , , , , , , , , and 9 other author(s). A-SSCC, page 169-172. IEEE, (2016)A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture., , and . IEEE J. Solid State Circuits, 40 (1): 254-260 (2005)An FPGA-based RNN-T Inference Accelerator with PIM-HBM., , , , , , and . FPGA, page 146-152. ACM, (2022)The Breakthrough Memory Solutions for Improved Performance on LLM Inference., , , , , , , , , and 13 other author(s). IEEE Micro, 44 (3): 40-48 (May 2024)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond., , , , , , , , , and 10 other author(s). HCS, page 1-26. IEEE, (2021)An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node Control., , , , , , , and . SoC, page 1-4. IEEE, (2006)A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC., , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)