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Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test.

, и . VLSI Design, стр. 262-267. IEEE Computer Society, (2011)

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Vasudharani Devanathan

Devanathan Raghunathan

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V Saile

V Ustinov

 

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Towards effective and compression-friendly test of memory interface logic., , , и . ITC, стр. 124-133. IEEE Computer Society, (2010)Towards adaptive test of multi-core RF SoCs., , , , , и . DATE, стр. 743-748. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems., , и . ICDCS Workshops, стр. 488-492. IEEE Computer Society, (2003)PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test., , , и . ITC, стр. 1-9. IEEE Computer Society, (2007)Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test., и . VLSI Design, стр. 262-267. IEEE Computer Society, (2011)New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation., , и . VLSID, стр. 363-368. IEEE Computer Society, (2015)Techniques to improve memory interface test quality for complex SoCs., и . ITC, стр. 1-10. IEEE Computer Society, (2011)Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms., , и . VLSI Design, стр. 351-356. IEEE Computer Society, (2007)ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs., , , , и . VLSID, стр. 342-347. IEEE Computer Society, (2014)Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage.. Asian Test Symposium, стр. 300-305. IEEE Computer Society, (2005)