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Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks.

, , and . CoRR, (2016)

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A Multi-Kernel Multi-Code Polar Decoder Architecture., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4413-4422 (2018)Fast and Efficient Convolutional Accelerator for Edge Computing., , and . IEEE Trans. Computers, 69 (1): 138-152 (2020)Implementation of Sparse Superposition Codes., and . IEEE Trans. Signal Process., 65 (9): 2421-2427 (2017)A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.. IEEE Trans. Circuits Syst. I Regul. Pap., 69 (5): 2203-2211 (2022)Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications., , , and . PDP, page 418-423. IEEE Computer Society, (2014)Improved Hybrid Design of Polar Codes and Multi-Kernel Polar Codes., , and . ISIT, page 1947-1951. IEEE, (2019)High-Throughput Low-Latency Encoder and Decoder for a Class of Generalized Reed-Solomon Codes for Short-Reach Optical Communications., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (4): 670-674 (2020)Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures., , , and . Integr., (2015)On the performance of polar codes for 5G eMBB control channel., , , and . ACSSC, page 1764-1768. IEEE, (2017)Input-distribution-aware parallel decoding of block codes., and . ISTC, page 1-5. IEEE, (2021)