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A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments., , , и . HPCC, стр. 58-67. IEEE, (2011)Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage., , , и . IVSW, стр. 61-66. IEEE, (2019)2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)., , , , , , и . DFT, стр. 1-4. IEEE, (2020)Fast Estimations of Failure Probability Over Long Time Spans., , , , , , , , и . NANOARCH, стр. 1-6. ACM, (2018)Variation-aware task allocation and scheduling for MPSoC., , , , и . ICCAD, стр. 598-603. IEEE Computer Society, (2007)Switch folding: network-on-chip routers with time-multiplexed output ports., , , и . DATE, стр. 344-349. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors., , и . IOLTS, стр. 110-115. IEEE, (2015)BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers., , , , , и . J. Parallel Distributed Comput., (2017)An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures., , , , , , и . ACM Trans. Archit. Code Optim., 13 (2): 22:1-22:26 (2016)ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers., , , , , и . MICRO, стр. 333-346. IEEE Computer Society, (2006)