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Optimising power efficiency in trace cache fetch unit., , , и . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)An edge-based heuristic for Steiner routing., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (12): 1563-1568 (1994)Compiler-guided leakage optimization for banked scratch-pad memories., , , и . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1136-1146 (2005)Distributed Fault Diagnosis in the Butterfly Parallel Processor., , , и . ICPP (1), стр. 172-175. Pennsylvania State University Press, (1989)Soft error and energy consumption interactions: a data cache perspective., , , , и . ISLPED, стр. 132-137. ACM, (2004)Exploiting program hotspots and code sequentiality for instruction cache leakage management., , , , и . ISLPED, стр. 402-407. ACM, (2003)Estimating influence of data layout optimizations on SDRAM energy consumption., , , , , и . ISLPED, стр. 40-43. ACM, (2003)Increasing on-chip memory space utilization for embedded chip multiprocessors through data compression., , и . CODES+ISSS, стр. 87-92. ACM, (2005)Intermediate-level vision tasks on a memory array architecture., и . Mach. Vis. Appl., 6 (1): 50-65 (1992)Exploring technology alternatives for nano-scale FPGA interconnects., , и . DAC, стр. 921-926. ACM, (2005)