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Disambiguation of "Calimera, Andrea"

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Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator.

, , , , and . DATE, page 1151-1154. IEEE, (2018)

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Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)

Michaela Andrea Fingas

Resultate nach radikaler Prostatektomie bei Patienten mit einem Prostatakarzinom Gleason 7-10. Uni Marburg, (2009)

Andrea Rupps

 

Other publications of authors with the same name

Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores., , , and . ICECS, page 598-601. IEEE, (2019)EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets., , and . AICAS, page 233-237. IEEE, (2020)Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks., , , , , , , , and . DATE, page 165-166. IEEE, (2012)Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits., , , and . ISLPED, page 217-220. ACM, (2008)Adaptive Test-Time Augmentation for Low-Power CPU., , , , and . CoRR, (2021)Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating., , , , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 214-225. Springer, (2011)Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks., and . DATE, page 114-119. IEEE, (2021)Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions., , , , and . ACM Great Lakes Symposium on VLSI, page 253-258. ACM, (2015)Power modeling and characterization of Graphene-based logic gates., , , and . PATMOS, page 223-226. IEEE, (2013)