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Disambiguation of "Mukhopadhyay, Saibal"

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Profit Aware Circuit Design Under Process Variations Considering Speed Binning.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (7): 806-815 (2008)

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Chandra Mukhopadhyay

Supratik Mukhopadhyay

Supratik Mukhopadhyay

Girindranath Mukhopadhyay

Prantik Mukhopadhyay

 

Other publications of authors with the same name

Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance., , and . DDECS, page 69-74. IEEE Computer Society, (2007)RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs., , , , , , , , , and 1 other author(s). DAC, page 101. ACM, (2019)WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous Platforms., , , and . DAC, page 1-6. IEEE, (2020)A 110nA synchronous boost regulator with autonomous bias gating for energy harvesting., and . CICC, page 1-4. IEEE, (2013)Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM., , and . CICC, page 433-436. IEEE, (2006)Automatic GDSII Generator for On-Chip Voltage Regulator for Easy Integration in Digital SoCs., , , and . ISLPED, page 1-6. IEEE, (2019)An Unsupervised Anomalous Event Detection Framework with Class Aware Source Separation., , and . ICASSP, page 2671-2675. IEEE, (2018)FocalNet - Foveal Attention for Post-processing DNN Outputs., and . IJCNN, page 1-8. IEEE, (2019)Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 174-183 (2008)MagNet: Discovering Multi-agent Interaction Dynamics using Neural Network., , , , and . ICRA, page 8158-8164. IEEE, (2020)