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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.

H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 91-C (4): 543-552 (2008)

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Esther Fujiwara

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A stable chip-ID generating physical uncloneable function using random address errors in SRAM.H. Fujiwara, M. Yabuuchi, Y. Tsukamoto, H. Nakano, T. Owada, H. Kawai, and K. Nii. SoCC, page 143-147. IEEE, (2012)12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.J. Chang, Y. Chen, W. Chan, S. Singh, H. Cheng, H. Fujiwara, J. Lin, K. Lin, J. Hung, R. Lee and 6 other author(s). ISSCC, page 206-207. IEEE, (2017)Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation.K. Nii, M. Yabuuchi, H. Fujiwara, H. Nakano, K. Ishihara, H. Kawai, and K. Arimoto. SoCC, page 519-524. IEEE, (2010)A dynamic body-biased SRAM with asymmetric halo implant MOSFETs.M. Yabuuchi, Y. Tsukamoto, H. Fujiwara, S. Tawa, K. Maekawa, M. Igarashi, and K. Nii. ISLPED, page 285-290. IEEE/ACM, (2011)Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application.Y. Tsukamoto, M. Yabuuchi, H. Fujiwara, K. Nii, C. Shin, and T. Liu. ISQED, page 270-274. IEEE, (2012)A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs.Y. Ishii, Y. Tsukamoto, K. Nii, H. Fujiwara, M. Yabuuchi, K. Tanaka, S. Tanaka, and Y. Shimazaki. ISSCC, page 236-238. IEEE, (2012)A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications.H. Fujiwara, Y. Chen, C. Lin, W. Wu, D. Sun, S. Wu, H. Liao, and J. Chang. A-SSCC, page 185-188. IEEE, (2016)A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.H. Noguchi, Y. Iguchi, H. Fujiwara, S. Okumura, Y. Morita, K. Nii, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 91-C (4): 543-552 (2008)20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices.M. Shih, S. Hsieh, P. Tsai, M. Lin, P. Tsung, E. Chang, J. Liang, S. Chang, C. Huang, Y. Nian and 14 other author(s). ISSCC, page 360-362. IEEE, (2024)A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection.H. Fujiwara, S. Okumura, Y. Iguchi, H. Noguchi, H. Kawaguchi, and M. Yoshimoto. VLSI Design, page 295-300. IEEE Computer Society, (2009)

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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.

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Esther Fujiwara

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Disambiguation of "Fujiwara, Hidehiro"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.

Please choose a person to relate this publication to

Esther Fujiwara

Other publications of authors with the same name

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A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing.