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Disambiguation of "Na, Taehui"

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A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (12): 1109-1113 (2015)

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Na Wei

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Other publications of authors with the same name

Offset Voltage Analysis and Enable Signal Rise Time Control Based Offset Reduction Technique of Current-Latched Sense Amplifier.. ICEIC, page 1-2. IEEE, (2021)Robust Offset-Cancellation Sensing-Circuit-Based Spin-Transfer-Torque Nonvolatile Flip-Flop.. IEEE Access, (2020)A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (12): 1109-1113 (2015)Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter., , , , and . ICECS, page 400-403. IEEE, (2015)High-performance low-power magnetic tunnel junction based non-volatile flip-flop., , , , , and . ISCAS, page 1953-1956. IEEE, (2014)A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 700-704 (2017)Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (12): 3376-3385 (2014)A Split-Path Sensing Circuit for Spin Torque Transfer MRAM., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (3): 193-197 (2014)Area-optimal sensing circuit designs in deep submicrometer STT-RAM., , , , and . ISCAS, page 1246-1249. IEEE, (2016)Reference-circuit analysis for high-bandwidth spin transfer torque random access memory., , , , and . ISLPED, page 365-370. IEEE, (2015)