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A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression.

, , и . IEEE Trans. Circuits Syst. II Express Briefs, 71 (8): 3940-3944 (августа 2024)

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Elham Rostamian

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3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison., , и . IEEE Trans. Computers, 71 (6): 1305-1319 (2022)A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression., , и . IEEE Trans. Circuits Syst. II Express Briefs, 71 (8): 3940-3944 (августа 2024)Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk., , , и . Qual. Reliab. Eng. Int., 33 (7): 1367-1385 (2017)Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches., , , и . EDCC, стр. 120-129. IEEE Computer Society, (2016)Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs., и . PDP, стр. 464-467. IEEE Computer Society, (2016)ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches., , и . ASP-DAC, стр. 173-178. ACM, (2019)STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation., , и . DATE, стр. 1484-1489. IEEE, (2020)Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation., , и . DATE, стр. 854-859. IEEE, (2019)