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3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison.

, , and . IEEE Trans. Computers, 71 (6): 1305-1319 (2022)

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3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison., , and . IEEE Trans. Computers, 71 (6): 1305-1319 (2022)A Low-Cost Fault-Tolerant Racetrack Cache Based on Data Compression., , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (8): 3940-3944 (August 2024)Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk., , , and . Qual. Reliab. Eng. Int., 33 (7): 1367-1385 (2017)Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches., , , and . EDCC, page 120-129. IEEE Computer Society, (2016)Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs., and . PDP, page 464-467. IEEE Computer Society, (2016)STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation., , and . DATE, page 1484-1489. IEEE, (2020)Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation., , and . DATE, page 854-859. IEEE, (2019)ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches., , and . ASP-DAC, page 173-178. ACM, (2019)