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A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling., , , , , , , , and . IEEE J. Solid State Circuits, 53 (4): 1139-1148 (2018)A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+., and . ISSCC, page 161-170. IEEE, (2006)A 1.2V, 3.5µW, 20MS/s, 8-bit comparator with dynamic-biasing preamplifier., and . ISCAS, IEEE, (2006)A 0.028% THD+N, 91% power-efficiency, 3-level PWM Class-D amplifier with a true differential front-end., , , , , , , , , and . ISSCC, page 96-98. IEEE, (2012)Op-amp swing reduction in sigma-delta modulators., and . ISCAS (1), page 525-528. IEEE, (2004)An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing., , , , , , , and . CICC, page 171-174. IEEE, (2009)74dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35dB opamp gain., , and . CICC, page 101-104. IEEE, (2008)A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS., , , , and . CICC, page 1-4. IEEE, (2009)A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement., and . ISCAS, page 733-736. IEEE, (2007)Mixed-Order Sturdy MASH Delta-Sigma Modulator., , , and . ISCAS, page 257-260. IEEE, (2007)