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A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip.

, , , , , , и . FPT, стр. 285-288. IEEE, (2007)

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Ursula Koike-Good

 

Другие публикации лиц с тем же именем

UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64., , и . FGCS, стр. 715-722. IOS Press, (1992)Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting., и . LP, том 264 из Lecture Notes in Computer Science, стр. 159-169. Springer, (1986)A Fleng Compiler for PIE64., , , и . IFIP PACT, том A-50 из IFIP Transactions, стр. 257-266. North-Holland, (1994)XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together., и . CICC, стр. 247-250. IEEE, (2005)Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA., , , , , , и . IEICE Trans. Inf. Syst., 90-D (12): 1947-1955 (2007)FPGAs with multidimensional mesh topology., , и . FPGA, стр. 223. ACM, (2006)Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity., , , , , , и . IEICE Trans. Inf. Syst., 87-D (8): 2004-2010 (2004)Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests., , и . GCCE, стр. 550-551. IEEE, (2015)Fast Speculative Search Engine on the Highly Parallel Computer EM-X., , , , и . SIGIR, стр. 390. ACM, (1998)The Instruction Set Architecture of the Inference Processor UNIRED II., , и . Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, том A-23 из IFIP Transactions, стр. 117-128. North-Holland, (1993)