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Disambiguation of "Blott, Michaela"

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Post-Training Quantization with Low-precision Minifloats and Integers on FPGAs.

, , , , , , and . CoRR, (2023)

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Irene Blottner

Steffen Blottner

Annemarie Blottner

Gerhard Blottner

Stefan Blöttner

 

Other publications of authors with the same name

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , and 1 other author(s). CoRR, (2018)DarwiNN: efficient distributed neuroevolution under communication constraints., , , and . GECCO Companion, page 141-142. ACM, (2020)LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications., , , and . FPL, page 291-297. IEEE, (2020)Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring., , and . LCTES, page 129-136. ACM, (2009)SYQ: Learning Symmetric Quantization for Efficient Deep Neural Networks., , , and . CVPR, page 4300-4309. Computer Vision Foundation / IEEE Computer Society, (2018)Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems., , and . FCCM, page 175-182. IEEE Computer Society, (2009)Efficient Error-Tolerant Quantized Neural Network Accelerators., , , , , , and . DFT, page 1-6. IEEE, (2019)Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA., , , and . GECCO, page 1125-1133. ACM, (2020)Dataflow architectures for 10Gbps line-rate key-value-stores., and . Hot Chips Symposium, page 1-25. IEEE, (2013)ACCL+: an FPGA-Based Collective Engine for Distributed Applications., , , , , , , and . OSDI, page 211-231. USENIX Association, (2024)