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Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.

, , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)

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A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , and . European Test Symposium, page 81-86. IEEE Computer Society, (2010)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , and . European Test Symposium, page 132-137. IEEE Computer Society, (2010)Intra-Cell Defects Diagnosis., , , , , , and . J. Electron. Test., 30 (5): 541-555 (2014)Parity prediction synthesis for nano-electronic gate designs., , , , , , and . ITC, page 820. IEEE Computer Society, (2010)Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption., , , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (1999)Comprehensive bridging fault diagnosis based on the SLAT paradigm., , , , , , , and . DDECS, page 264-269. IEEE Computer Society, (2009)Failure Analysis and Test Solutions for Low-Power SRAMs., , , , , , , and . Asian Test Symposium, page 459-460. IEEE Computer Society, (2011)Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies., , , , and . DAC, page 857-862. ACM, (2005)A new test pattern generation method for delay fault testing., , , , and . VTS, page 296-301. IEEE Computer Society, (1996)Defect Analysis for Delay-Fault BIST in FPGAs., , , and . IOLTS, page 124-128. IEEE Computer Society, (2003)