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Disambiguation of "Taco, Ramiro"

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Dynamic gate-level body biasing for subthreshold digital design.

, , and . LASCAS, page 1-4. IEEE, (2014)

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Taco Kuiper

Theofanis Tacou

Ramiro Alberio

Ramiro Brenes

Ramiro Medina

 

Other publications of authors with the same name

Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells., , , , , and . LASCAS, page 1-4. IEEE, (2022)Dynamic gate-level body biasing for subthreshold digital design., , and . LASCAS, page 1-4. IEEE, (2014)Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories., , , , and . LASCAS, page 1-4. IEEE, (2022)Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (9): 1639-1643 (2020)Dual Mode Logic Address Decoder., , , , and . ISCAS, page 1-5. IEEE, (2020)Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications., , , , , and . LASCAS, page 1-4. IEEE, (2020)High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator., , , , and . LASCAS, page 1-4. IEEE, (2021)RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies., , , , , , and . LASCAS, page 1-4. IEEE, (2021)Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths., , , , and . ISCAS, page 1. IEEE, (2021)Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology., , , and . ISCAS, page 41-44. IEEE, (2016)