From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS., , , , и . ESSCIRC, стр. 202-205. IEEE, (2008)Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends., , , , , и . IEEE J. Solid State Circuits, 36 (11): 1636-1646 (2001)Desensitized design of MOS low noise amplifiers by Rn minimization., , , , и . ICECS, стр. 619-622. IEEE, (2004)A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS., , , , и . CICC, стр. 1-4. IEEE, (2009)A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS., , , , и . ESSCIRC, стр. 535-538. IEEE, (2005)A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS., , и . ESSCIRC, стр. 352-355. IEEE, (2007)Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process., , , , , , , , , и 1 other автор(ы). CICC, стр. 617-620. IEEE, (2003)8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS., , , и . CICC, стр. 625-628. IEEE, (2004)A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS., , , , , и . ISSCC, стр. 70-72. IEEE, (2012)Measurement and modeling of noise parameters for desensitized low noise amplifiers., , , , и . CICC, стр. 387-390. IEEE, (2004)