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Hierarchical test generation under architectural level functional constraints.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (9): 1144-1151 (1996)

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Hierarchical test generation under architectural level functional constraints., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (9): 1144-1151 (1996)Testability analysis based on structural and behavioral information., and . VTS, page 139-146. IEEE Computer Society, (1993)ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults., and . ITC, page 729-738. IEEE Computer Society, (1991)Architectural Level Test Generation and Fault Simulation. University of Illinois Urbana-Champaign, USA, (1992)A comparative study of design for testability methods using high-level and gate-level descriptions., , and . ICCAD, page 620-624. IEEE Computer Society / ACM, (1992)An architectural level test generator based on nonlinear equation solving., and . J. Electron. Test., 4 (2): 137-150 (1993)Impact of high level functional constraints on testability., , and . VTS, page 309-312. IEEE Computer Society, (1993)Design for Testability Using Architectural Descriptions., , and . ITC, page 752-761. IEEE Computer Society, (1992)An Architectural Level Test Generator for a Hierarchical Design Environment., and . FTCS, page 44-51. IEEE Computer Society, (1991)Addressing design for testability at the architectural level., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (7): 920-934 (1994)