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Improving approximate-TMR using multi-objective optimization genetic algorithm., , , , , , и . LATS, стр. 1-6. IEEE, (2018)Synthesis of threshold logic gates to nanoelectronics., , , и . SBCCI, стр. 1-6. IEEE, (2013)Logic IP for Low-Cost IC Design in Advanced CMOS Nodes., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 28 (2): 585-595 (2020)From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (2): 520-532 (2020)Read-polarity-once Boolean functions., , , и . SBCCI, стр. 1-6. IEEE, (2013)Virtual characterization for exhaustive DFM evaluation of logic cell libraries., , и . ISQED, стр. 93-98. IEEE, (2017)Efficient method to compute minimum decision chains of Boolean functions., , , и . ACM Great Lakes Symposium on VLSI, стр. 419-422. ACM, (2011)A Simple and Effective Heuristic Method for Threshold Logic Identification., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (5): 1023-1036 (2018)Functional composition: A new paradigm for performing logic synthesis., , и . ISQED, стр. 236-242. IEEE, (2012)Methodology for achieving best trade-off of area and fault masking coverage in ATMR., , , , , и . LATW, стр. 1-6. IEEE, (2014)