( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Efficient method to compute minimum decision chains of Boolean functions.

, , , и . ACM Great Lakes Symposium on VLSI, стр. 419-422. ACM, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Maristella Ribas

Cesar Ribas Cezar

Renato Hasche

Renato Meola

Renato Pasold

 

Другие публикации лиц с тем же именем

A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design., , , и . ISPD, стр. 185-192. ACM, (2015)SwitchCraft: a framework for transistor network design., , , , , и . SBCCI, стр. 49-53. ACM, (2010)Performance evaluation of optimized transistor networks built using independent-gate FinFET., , , , и . LASCAS, стр. 227-230. IEEE, (2016)Graph-Based Transistor Network Generation Method for Supergate Design., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 692-705 (2016)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5126-5130 (2022)ATMR design by construction based on two-level ALS., , , , и . SBCCI, стр. 1-6. IEEE, (2023)On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design., , , , , и . LATS, стр. 135-140. IEEE, (2016)Exact lower bound for the number of switches in series to implement a combinational logic cell., , , и . ICCD, стр. 357-362. IEEE Computer Society, (2005)Improvements on the detection of false paths by using unateness and satisfiability., , , и . SBCCI, стр. 192-197. ACM, (2010)Area impact analysis of via-configurable regular fabric for digital integrated circuit design., , , , , и . SBCCI, стр. 103-108. ACM, (2011)