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A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction.

A. Elmallah, J. Zhu, A. Khashaba, K. Megawer, A. Elkholy, and P. Hanumolu. CICC, page 1-2. IEEE, (2021)

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Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

Other publications of authors with the same name

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.G. Shu, W. Choi, S. Saxena, S. Kim, M. Talegaonkar, R. Nandwana, A. Elkholy, D. Wei, T. Nandi, and P. Hanumolu. ISSCC, page 398-399. IEEE, (2016)A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.S. Saxena, G. Shu, R. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. Kim, W. Choi, and P. Hanumolu. VLSIC, page 352-. IEEE, (2015)10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS.W. Liu, P. Assem, Y. Lei, P. Hanumolu, and R. Pilawa-Podgurski. ISSCC, page 182-183. IEEE, (2017)A low spur fractional-N frequency synthesizer architecture.V. Kratyuk, P. Hanumolu, U. Moon, and K. Mayaram. ISCAS (3), page 2807-2810. IEEE, (2005)A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity.A. Elshazly, R. Inti, M. Talegaonkar, and P. Hanumolu. VLSIC, page 188-189. IEEE, (2012)Area efficient phase calibration of a 1.6 GHz multiphase DLL.A. Agrawal, P. Hanumolu, and G. Wei. CICC, page 1-4. IEEE, (2011)A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.S. Asl, S. Saxena, P. Hanumolu, K. Mayaram, and T. Fiez. CICC, page 1-4. IEEE, (2011)Digital clock and data recovery circuit design: Challenges and tradeoffs.M. Talegaonkar, R. Inti, and P. Hanumolu. CICC, page 1-8. IEEE, (2011)A 0.7V time-based inductor for fully integrated low bandwidth filter applications.B. Salz, M. Talegaonkar, G. Shu, A. Elmallah, R. Nandwana, B. Sahoo, and P. Hanumolu. CICC, page 1-4. IEEE, (2017)An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing.S. Kwon, P. Hanumolu, S. Kim, S. Lee, S. You, H. Park, J. Kim, and U. Moon. CICC, page 171-174. IEEE, (2009)

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Disambiguation of "Hanumolu, Pavan Kumar"

Please choose a person to relate this publication to

Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

Other publications of authors with the same name

Disambiguation