( en | de | ru )

 

Disambiguation of "Reddy, Sudhakar M."

Author of the publication

copydeleteadd this publication to your clipboard
A Cube-Aware Compaction Method for Scan ATPG.

, , , , , and . VLSI Design, page 98-103. IEEE Computer Society, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

Other publications of authors with the same name

Design of Easily Testable Microprocessors : A Case Study., and . ITC, page 480-483. IEEE Computer Society, (1982)On the Design of Random Pattern Testable PLAs., and . ITC, page 688-695. IEEE Computer Society, (1986)At-speed scan test with low switching activity., , , and . VTS, page 177-182. IEEE Computer Society, (2010)On multiple bridging faults., and . VTS, page 221-226. IEEE Computer Society, (2010)On Improving Fault Diagnosis for Synchronous Sequential Circuits., and . DAC, page 504-509. ACM Press, (1994)INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning., and . DAC, page 80-85. ACM Press, (1993)Functional Broadside Tests with Minimum and Maximum Switching Activity., and . J. Low Power Electron., 4 (3): 429-437 (2008)Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits., and . IEEE Trans. Dependable Secur. Comput., 6 (3): 231-240 (2009)On synchronizable circuits and their synchronizing sequences., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (9): 1086-1092 (2000)Theorems for identifying undetectable faults in partial-scan circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (8): 1092-1097 (2003)