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A Cube-Aware Compaction Method for Scan ATPG.

, , , , , и . VLSI Design, стр. 98-103. IEEE Computer Society, (2014)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

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On the Design of Random Pattern Testable PLAs., и . ITC, стр. 688-695. IEEE Computer Society, (1986)Design of Easily Testable Microprocessors : A Case Study., и . ITC, стр. 480-483. IEEE Computer Society, (1982)Minimal area test points for deterministic patterns., , , , , и . ITC, стр. 1-7. IEEE, (2016)Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times., и . IEEE Trans. Computers, 51 (4): 409-419 (2002)Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits., и . IEEE Trans. Computers, 35 (8): 742-754 (1986)Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions., и . IEEE Trans. Computers, 23 (1): 98-100 (1974)A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines., и . IEEE Trans. Computers, 27 (10): 927-934 (1978)On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit., и . IEEE Trans. Computers, 53 (9): 1121-1133 (2004)INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning., и . DAC, стр. 80-85. ACM Press, (1993)On Improving Fault Diagnosis for Synchronous Sequential Circuits., и . DAC, стр. 504-509. ACM Press, (1994)