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Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array.

, , , , , and . Journal of Circuits, Systems, and Computers, 24 (3): 1550043:1-1550043:21 (2015)

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An ASIC implementation of JPEG2000 codec., , , and . CICC, page 691-694. IEEE, (2005)MapReduce inspired loop mapping for coarse-grained reconfigurable architecture., , , and . Sci. China Inf. Sci., 57 (12): 1-14 (2014)Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3081-3094 (2018)Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2271-2283 (2019)ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration., , , , , , , , , and . IEEE J. Solid State Circuits, 58 (1): 243-255 (2023)Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation., , , , , and . IEEE Trans. Wirel. Commun., 19 (2): 1025-1037 (2020)A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating., , , , and . ASP-DAC, page 229-234. ACM, (2021)A Fast-locking and Wide-range Reversible SAR DLL., , and . ISCAS, page 992-995. IEEE, (2009)A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems., , , , and . ASICON, page 224-227. IEEE, (2011)A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions., , , , , , and . AICAS, page 1-5. IEEE, (2023)