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Hardware architectures for successive cancellation decoding of polar codes.

, , , and . ICASSP, page 1665-1668. IEEE, (2011)

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Hardware architectures for successive cancellation decoding of polar codes., , , and . ICASSP, page 1665-1668. IEEE, (2011)A Semi-Parallel Successive-Cancellation Decoder for Polar Codes., , , and . IEEE Trans. Signal Process., 61 (2): 289-299 (2013)Stochastic Chase Decoding of Reed-Solomon Codes., , , and . IEEE Commun. Lett., 14 (9): 863-865 (2010)A 8.34 nW Wake-Up Receiver Achieving -50dBm Sensitivity at 2.4GHz., , , and . NEWCAS, page 1-4. IEEE, (2023)A highly parallel Turbo Product Code decoder without interleaving resource., , , , and . SiPS, page 1-6. IEEE, (2008)Hardware implementation of a soft cancellation decoder for polar codes., , , and . DASIP, page 1-8. IEEE, (2015)Custom Low Power Processor for Polar Decoding., , , , , and . ISCAS, page 1-5. IEEE, (2018)An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes., , , , and . LCPC, volume 9519 of Lecture Notes in Computer Science, page 303-317. Springer, (2015)Partial sums generation architecture for successive cancellation decoding of polar codes., , , and . SiPS, page 407-412. IEEE, (2013)Software polar decoder on an embedded processor., , and . SiPS, page 180-185. IEEE, (2014)