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Disambiguation of "Fesquet, Laurent"

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Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression.

, , , and . EBCCSP, page 1-6. IEEE, (2020)

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Laurent Bartholdi

Thomas Laurent

Laurent Herschke

Thomas Laurent

Laurent Ntahuga

 

Other publications of authors with the same name

Self-timed Ring based True Random Number Generator: Threat model and countermeasures., , , and . IVSW, page 31-38. IEEE, (2017)A Digital Event-Based Strategy for ASK demodulation., , and . VLSI-SoC, page 244-245. IEEE, (2019)Time-to-Digital Converters: A Literature Review and New Perspectives., , and . EBCCSP, page 1-8. IEEE, (2019)Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society., , and . LASCAS, page 1-4. IEEE, (2018)Implementing Snoop-Coherence Protocol for Future SMP Architectures., , and . Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 745-752. Springer, (1999)From High-Level Synthesis to Bundled-Data Circuits., , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 200-212. Springer, (2020)IIR digital filtering of non-uniformly sampled signals via state representation., and . Signal Process., 90 (10): 2811-2821 (2010)An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems., , , and . ICECS, page 765-768. IEEE, (2018)Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors., , and . ISVLSI, page 290-295. IEEE Computer Society, (2017)A New Class of Asynchronous A/D Converters Based on Time Quantization., , , and . ASYNC, page 196-205. IEEE Computer Society, (2003)