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Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems.

, , and . FCCM, page 175-182. IEEE Computer Society, (2009)

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LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications., , , and . FPL, page 291-297. IEEE, (2020)Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , and 1 other author(s). CoRR, (2018)DarwiNN: efficient distributed neuroevolution under communication constraints., , , and . GECCO Companion, page 141-142. ACM, (2020)Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems., , and . FCCM, page 175-182. IEEE Computer Society, (2009)Efficient Error-Tolerant Quantized Neural Network Accelerators., , , , , , and . DFT, page 1-6. IEEE, (2019)Dataflow architectures for 10Gbps line-rate key-value-stores., and . Hot Chips Symposium, page 1-25. IEEE, (2013)Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA., , , and . GECCO, page 1125-1133. ACM, (2020)SYQ: Learning Symmetric Quantization for Efficient Deep Neural Networks., , , and . CVPR, page 4300-4309. Computer Vision Foundation / IEEE Computer Society, (2018)ACCL+: an FPGA-Based Collective Engine for Distributed Applications., , , , , , , and . OSDI, page 211-231. USENIX Association, (2024)Corrigendum: Applications and techniques for fast machine learning in science., , , , , , , , , and 37 other author(s). Frontiers Big Data, (2024)