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Disambiguation of "Portal, Jean-Michel"

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Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks.

, , , , , , and . AICAS, page 288-292. IEEE, (2019)

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Jean-Michel Langlais

Jean-Michel Dengler

Jean-Michel Grossenbacher

Jean-Michel Autebert

Jean-Michel Ayache

 

Other publications of authors with the same name

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells., , , , , , , , , and 4 other author(s). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)A Discussion on Test Pattern Generation for FPGA - Implemented Circuits., , , , and . J. Electron. Test., 17 (3-4): 283-290 (2001)DCG-FGT transistor: Retention study of Floating Gate charge., , , , , and . MWSCAS, page 825-827. IEEE, (2013)Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization., , , , , , , , , and 4 other author(s). IRPS, page 1-6. IEEE, (2021)A Self-referenced and regulated sensing solution for PCM with OTS selector., , , , , , and . VLSI-SoC, page 1-6. IEEE, (2021)1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing., , , , , , , , , and 10 other author(s). IMW, page 1-4. IEEE, (2022)Improvement of a VCO concept for low energy particule detection and recognition., , , , and . LATW, page 1-4. IEEE, (2014)Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study., , , and . ETW, page 146-151. IEEE Computer Society, (1999)A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories., , and . ITC, page 1-10. IEEE Computer Society, (2008)Minimizing the Number of Test Configurations for Different FPGA Families., , , and . Asian Test Symposium, page 363-368. IEEE Computer Society, (1999)