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Sub-pJ consumption and short latency time in RRAM arrays for high endurance applications., , , , , , , , , and 2 other author(s). IRPS, page 2-1. IEEE, (2018)High speed and high-area efficiency non-volatile look-up table design based on magnetic tunnel junction., , , and . NVMTS, page 1-4. IEEE, (2017)Low Power In-Memory Implementation of Ternary Neural Networks with Resistive RAM-Based Synapse., , , , , , , , and . AICAS, page 136-140. IEEE, (2020)OTS selector devices: Material engineering for switching performance., , , , , , , , and . ICICDT, page 113-116. IEEE, (2018)Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization., , , , , , , , , and 4 other author(s). IRPS, page 1-6. IEEE, (2021)In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical Applications., , , , , , , and . DATE, page 690-695. IEEE, (2020)High density SOT-MRAM memory array based on a single transistor., , , and . NVMTS, page 1-3. IEEE, (2018)Insect-Inspired Elementary Motion Detection Embracing Resistive Memory and Spiking Neural Networks., , , , , , and . Living Machines, volume 10928 of Lecture Notes in Computer Science, page 115-128. Springer, (2018)Carbon electrode for Ge-Se-Sb based OTS selector for ultra low leakage current and outstanding endurance., , , , , , , , , and 2 other author(s). IRPS, page 6. IEEE, (2018)MRAM: from STT to SOT, for security and memory., , , , , , , , and . DCIS, page 1-6. IEEE, (2018)