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Bayesian network early reliability evaluation analysis for both permanent and transient faults., , , , , , , and . IOLTS, page 7-12. IEEE, (2015)A Digital Twin for Maritime Situational Awareness., , , , , , , and . BDCAT, page 26:1-26:2. ACM, (2023)Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs., , , , , , , , , and 2 other author(s). DSN Workshops, page 6-9. IEEE Computer Society, (2018)Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs., , , , and . ISPASS, page 54-63. IEEE Computer Society, (2018)Microprocessor reliability-performance tradeoffs assessment at the microarchitecture level., , , , and . VTS, page 1-6. IEEE Computer Society, (2016)A Scalable System for Maritime Route and Event Forecasting., , , , , , , , , and 2 other author(s). EDBT, page 762-769. OpenProceedings.org, (2024)A Bayesian model for system level reliability estimation., , , , , , , and . ETS, page 1-2. IEEE, (2015)RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU., , , , , , and . DSN Workshops, page 117-120. IEEE Computer Society, (2017)Performance-aware reliability assessment of heterogeneous chips., , , and . VTS, page 1-6. IEEE Computer Society, (2017)Accelerated online error detection in many-core microprocessor architectures., , , and . VTS, page 1-6. IEEE Computer Society, (2014)