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Disambiguation of "Huang, Ru"

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Device-Architecture Co-optimization for RRAM-based In-memory Computing.

, , , , , , , and . ASICON, page 1-4. IEEE, (2023)

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Ru-Jin Huang

Ru Zhang

Ru Xie

Ru Hao

Tomasz Ru

 

Other publications of authors with the same name

Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System., , , , , , , , and . AICAS, page 1-2. IEEE, (2023)Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life., , and . ICICDT, page 1-3. IEEE, (2016)A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme., , , , , , , and . CICC, page 1-2. IEEE, (2022)Compact modeling and simulation of accelerated circuit aging., , , , , , and . CICC, page 1-4. IEEE, (2018)The design of energy-saving filtering mechanism for sensor networks., and . ICMLC, page 79-85. IEEE, (2010)20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC., , , , , , and . ISSCC, page 314-316. IEEE, (2020)Compact Modeling of Phase Change Memory with Parameter Extractions., , , , , , , , and . ESSDERC, page 308-311. IEEE, (2022)First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology., , , , , , , , , and 8 other author(s). ESSDERC, page 13-16. IEEE, (2023)Session 16 Overview: Computation in Memory Memory Subcommittee., , and . ISSCC, page 244-245. IEEE, (2021)A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting., , , , , , , , , and . ISSCC, page 346-347. IEEE, (2023)