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NVM duet: unified working memory and persistent store architecture.

, , , , and . ASPLOS, page 455-470. ACM, (2014)

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Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices., , , , , , , , , and 3 other author(s). VLSI Circuits, page 166-. IEEE, (2019)A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors., , , , , , , , , and 12 other author(s). ISSCC, page 388-390. IEEE, (2019)DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors., , , , , , , , , and 7 other author(s). ISSCC, page 494-496. IEEE, (2018)VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layers., , and . ICCAD, page 283-290. IEEE, (2017)Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN)., , , , , , , and . ESSCIRC, page 241-244. IEEE, (2019)5.9 A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel., , , , , , , , , and 3 other author(s). ISSCC, page 110-112. IEEE, (2020)A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification., , , , , , , and . IEEE J. Solid State Circuits, 58 (11): 3266-3274 (November 2023)Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in Memory., , , , and . DATE, page 1-6. IEEE, (2023)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning., , , , , , , , , and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)